18357204. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Kiheung Kim of Suwon-si (KR)

Taeyoung Oh of Suwon-si (KR)

Jongcheol Kim of Suwon-si (KR)

Kyungho Lee of Suwon-si (KR)

Hyongryol Hwang of Suwon-si (KR)

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18357204 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

Simplified Explanation

The semiconductor memory device described in the patent application includes a memory cell array with multiple memory cell rows, a row hammer management circuit, and a control logic circuit.

The row hammer management circuit stores counted values in count cells of each memory cell row as count data, based on an active command applied to the control logic circuit at a first time point. It also performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row, update the count data, and write the updated count data in response to a precharge command applied at a second time point after a first command applied to the control logic circuit.

  • The memory cell array consists of multiple memory cell rows.
  • The row hammer management circuit stores counted values in count cells of each memory cell row as count data.
  • The count data is based on an active command applied to the control logic circuit at a first time point.
  • The row hammer management circuit performs an internal read-update-write operation to update the count data of a target memory cell row.
  • The updated count data is written back into the count cells of the target memory cell row in response to a precharge command applied at a second time point.

Potential applications of this technology:

  • Semiconductor memory devices used in various electronic devices such as computers, smartphones, and tablets.
  • Memory systems that require efficient management of memory cell rows.

Problems solved by this technology:

  • Row hammer issues, which refer to the disturbance of adjacent memory cells caused by repeated accessing of a specific memory cell row.
  • Inefficient management of memory cell rows and count data.

Benefits of this technology:

  • Improved reliability and performance of semiconductor memory devices.
  • Efficient management of memory cell rows and count data.
  • Prevention of row hammer issues and disturbance of adjacent memory cells.


Original Abstract Submitted

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

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