18356771. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Seungryong Oh of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18356771 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes multiple chip structures on a substrate, with an encapsulant covering them. The third chip structure overlaps a portion of the space between the first and second chip structures, with an upper chip structure on top.
- The semiconductor package includes a substrate, first, second, and third chip structures, and an encapsulant.
- The third chip structure overlaps a portion of the space between the first and second chip structures.
- The upper chip structure is on top of the lower chip structure in the third chip structure.
Potential Applications
This technology could be applied in:
- Advanced electronic devices
- Semiconductor manufacturing industry
Problems Solved
This technology helps in:
- Improving chip structure integration
- Enhancing semiconductor package reliability
Benefits
The benefits of this technology include:
- Increased efficiency in semiconductor packaging
- Enhanced performance of electronic devices
Potential Commercial Applications
This technology could be commercially applied in:
- Consumer electronics
- Automotive electronics
Possible Prior Art
One possible prior art could be the use of multi-chip modules in semiconductor packaging.
Unanswered Questions
How does this technology impact the overall cost of semiconductor packaging?
The abstract does not provide information on the cost implications of this technology.
What are the environmental implications of using this semiconductor packaging technology?
The abstract does not address the environmental impact of implementing this technology.
Original Abstract Submitted
A semiconductor package includes a substrate; a first chip structure on the substrate and having a first thickness in a first direction; a second chip structure on the substrate adjacent to the first chip structure along a second direction and having a second thickness in the first direction; a third chip structure on the substrate and adjacent to the first chip structure and the second chip structure in a third direction perpendicular to the second direction; and an encapsulant covering the first chip structure, the second chip structure, and the third chip structure, wherein the third chip structure includes a lower chip structure that overlaps a first portion of a space between the first chip structure and the second chip structure in the third direction, and an upper chip structure on the lower chip structure such that a second portion of the space is exposed in the third direction.
