18350405. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
HYUNGJUN Jeon of SUWON-SI (KR)
KWANGJIN Moon of SUWON-SI (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18350405 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
The semiconductor package described in the patent application consists of two chips, with the second chip bonded to and electrically connected to the front surface of the first chip. The first chip includes a semiconductor substrate with a through via, a semiconductor element on the front surface, and a back side wiring layer with a power wiring on the rear surface connected to the semiconductor element. The second chip has a through via larger than the one in the first chip.
- The semiconductor package includes two chips bonded together, with the second chip having a larger through via size than the first chip.
- The first chip features a semiconductor substrate with a through via, a semiconductor element, and a back side wiring layer with a power wiring.
- The second chip is connected to the front surface of the first chip and has a larger through via size.
Potential Applications: - This technology could be used in the manufacturing of advanced semiconductor packages for various electronic devices. - It may find applications in the development of high-performance computing systems and integrated circuits.
Problems Solved: - Enhances the electrical connectivity and performance of semiconductor packages. - Allows for more efficient power distribution within electronic devices.
Benefits: - Improved electrical connections between chips. - Enhanced power distribution capabilities. - Increased performance and reliability of electronic devices.
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Performance This technology could be utilized in the production of high-end consumer electronics, data centers, and telecommunications equipment, improving overall performance and reliability.
Questions about Semiconductor Package Technology: 1. How does the size of the through vias impact the performance of the semiconductor package?
- The size of the through vias can affect the electrical connectivity and power distribution within the package, ultimately influencing its overall performance.
2. What are the potential challenges in implementing this advanced semiconductor packaging technology in mass production?
- Some challenges may include optimizing manufacturing processes, ensuring compatibility with existing systems, and managing costs effectively.
Original Abstract Submitted
A semiconductor package includes a first chip and a second chip bonded to and electrically connected to a front surface of the first chip. The first chip includes a first semiconductor substrate including a first through via, a semiconductor element positioned on a front surface of the first semiconductor substrate, and a back side wiring layer including a back side power wiring positioned on a rear surface of the first semiconductor substrate and electrically connected to the semiconductor element unit. The second chip includes a second through via having a size greater than a size of the first through via.
