18347964. INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS simplified abstract (Intel Corporation)

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INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS

Organization Name

Intel Corporation

Inventor(s)

JAMES Valerio of NORTH PLAINS OR (US)

VASANTH Ranganathan of EL DORADO HILLS CA (US)

JOYDEEP Ray of FOLSOM CA (US)

PRADEEP Ramani of MILPITAS CA (US)

INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18347964 titled 'INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS

Simplified Explanation

The patent application describes a graphics processing device that includes compute units, a cache, and circuitry.

  • The compute units execute a workload.
  • The cache is coupled with the compute units.
  • The circuitry is coupled with the cache and compute units.
  • In the event of a cache miss for a read from a first cache, the circuitry broadcasts an event within the graphics processor device to identify the data associated with the cache miss.
  • The event is received by a second compute unit in the set of compute units.
  • The second compute unit prefetches the identified data into a second cache that is local to the second compute unit before attempting to read the instruction or data by the second thread.

Potential applications of this technology:

  • Graphics processing devices in gaming consoles, computers, and mobile devices.
  • High-performance computing systems that require efficient data access and processing.

Problems solved by this technology:

  • Reduces cache misses, which can significantly impact performance in graphics processing.
  • Improves data access and processing efficiency by prefetching data into a local cache.

Benefits of this technology:

  • Improved performance and responsiveness in graphics processing.
  • Enhanced efficiency in high-performance computing systems.
  • Reduced latency in data access and processing.


Original Abstract Submitted

A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. The circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and prefetch the data identified by the event into a second cache that is local to the second compute unit before an attempt to read the instruction or data by the second thread.

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