18347129. OVERLAY CORRECTION METHOD, AND EXPOSURE METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD INCLUDING OVERLAY CORRECTION METHOD simplified abstract (Samsung Electronics Co., Ltd.)

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OVERLAY CORRECTION METHOD, AND EXPOSURE METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD INCLUDING OVERLAY CORRECTION METHOD

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Wooyong Jung of Suwon-si (KR)

Dohun Kim of Suwon-si (KR)

Joonhyun Kim of Suwon-si (KR)

Jeongjin Lee of Suwon-si (KR)

Seungyoon Lee of Suwon-si (KR)

Chan Hwang of Suwon-si (KR)

OVERLAY CORRECTION METHOD, AND EXPOSURE METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD INCLUDING OVERLAY CORRECTION METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18347129 titled 'OVERLAY CORRECTION METHOD, AND EXPOSURE METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD INCLUDING OVERLAY CORRECTION METHOD

Simplified Explanation

The abstract describes an overlay correction method for correcting overlay due to wafer table degradation, as well as an exposure method and semiconductor device manufacturing method that include this overlay correction method. The method involves acquiring leveling data, converting it into overlay data, splitting shots into sub-shots, extracting a model for each sub-shot, and correcting overlay parameters in real-time during the exposure process.

  • Acquiring leveling data regarding a wafer
  • Converting leveling data into overlay data
  • Splitting shots into sub-shots via shot size split
  • Extracting a model for each sub-shot from overlay data
  • Correcting overlay parameters of exposure equipment in real-time

Potential Applications

This technology can be applied in semiconductor manufacturing processes where precise overlay correction is crucial for ensuring the quality and performance of semiconductor devices.

Problems Solved

1. Correcting overlay due to wafer table degradation 2. Ensuring accurate alignment of layers in semiconductor manufacturing

Benefits

1. Improved accuracy in overlay correction 2. Real-time correction for enhanced efficiency 3. Higher quality and performance of semiconductor devices

Potential Commercial Applications

"Real-Time Overlay Correction Method for Semiconductor Manufacturing" can be utilized in the semiconductor industry for improving production processes and ensuring high-quality semiconductor devices.

Possible Prior Art

One possible prior art could be the use of feedforward methods in overlay correction processes in semiconductor manufacturing. Additionally, there may be patents related to shot size split techniques for improving overlay accuracy.

What are the limitations of the overlay correction method described in the patent application?

The patent application does not mention any potential limitations or challenges that may arise when implementing the overlay correction method. It would be helpful to know if there are any specific constraints or drawbacks to consider.

How does the real-time overlay correction method compare to traditional overlay correction techniques?

The patent application does not provide a direct comparison between the real-time overlay correction method and traditional overlay correction techniques. It would be beneficial to understand the advantages and disadvantages of this new method compared to existing approaches.


Original Abstract Submitted

Provided are an overlay correction method for effectively correcting an overlay due to degradation of a wafer table, and an exposure method and a semiconductor device manufacturing method, which include the overlay correction method, wherein the overlay correction method includes acquiring leveling data regarding a wafer, converting the leveling data into overlay data, splitting a shot into sub-shots via shot size split, extracting a model for each sub-shot from the overlay data, and correcting an overlay parameter of exposure equipment on the basis of the model for each sub-shot, wherein the correction of the overlay parameter is applied in real time to an exposure process for the wafer in a feedforward method.