18339904. Mechanism To Enhance PCIe Generation Switching (QUALCOMM Incorporated)
Contents
Mechanism To Enhance PCIe Generation Switching
Organization Name
Inventor(s)
Santhosh Reddy Akavaram of Hyderabad (IN)
Prakhar Srivastava of Lucknow (IN)
Ravindranath Doddi of Hyderabad (IN)
Rajendra Varma Pusapati of Hyderabad (IN)
Sonali Jabreva of Firozabad (IN)
Mechanism To Enhance PCIe Generation Switching
This abstract first appeared for US patent application 18339904 titled 'Mechanism To Enhance PCIe Generation Switching
Original Abstract Submitted
Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.
