18339132. DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURES simplified abstract (APPLE INC.)
DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURES
Organization Name
Inventor(s)
Sanjay Dabral of Cupertino CA (US)
Kunzhong Hu of Cupertino CA (US)
Raymundo M. Camenforte of San Jose CA (US)
DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18339132 titled 'DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURES
Simplified Explanation
The patent application describes multi-die structures with die-to-die routing, where each die is patterned into the same semiconductor substrate. The dies can be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals can be formed to accommodate the die-to-die routing, and programmable dicing can be used. The technology can also be applied to three-dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.
- Multi-die structures with die-to-die routing are described in the patent application.
- Each die is patterned into the same semiconductor substrate.
- The dies can be interconnected with die-to-die routing during back-end wafer processing.
- Partial metallic seals can be formed to accommodate the die-to-die routing.
- Programmable dicing can be used.
- The technology can be extended to three-dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.
Potential Applications
- Semiconductor manufacturing industry
- Electronics industry
- Integrated circuit design and production
Problems Solved
- Enables efficient interconnection of multiple dies on a single semiconductor substrate
- Allows for die-to-die routing during back-end wafer processing
- Provides flexibility in forming partial metallic seals and programmable dicing
Benefits
- Improved integration and connectivity of multiple dies
- Enhanced functionality and performance of integrated circuits
- Increased flexibility in manufacturing and design processes
Original Abstract Submitted
Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.
