18338037. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18338037 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a package substrate, two semiconductor chips, a first molding member, and a second molding member. The first molding member covers the two semiconductor chips and includes different ratios of filler material in its different portions.
- The semiconductor package includes a package substrate, two semiconductor chips, and two molding members.
- The first molding member covers the two semiconductor chips and has a higher ratio of filler material in one portion compared to the other.
- The second molding member is on top of the first molding member.
- Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
- Problems Solved
- Ensures proper protection and insulation of semiconductor chips
- Helps in maintaining the structural integrity of the semiconductor package
- Benefits
- Improved reliability of semiconductor devices
- Enhanced performance due to better protection of semiconductor chips
Original Abstract Submitted
A semiconductor package includes a package substrate, a first semiconductor chip and a second semiconductor chip on the package substrate in adjacent, spaced-apart relationship, a first molding member on the package substrate and covering the first semiconductor chip and the second semiconductor chip, and a second molding member on the first molding member. The first molding member includes a first molding portion on the first semiconductor chip and a second molding portion between the first and second semiconductor chips. A ratio per unit volume of filler material included in the first molding portion is greater than a ratio per unit volume of filler material included in the second molding portion.
