18337113. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Sang-Sick Park of Suwon-si (KR)
Un-Byoung Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18337113 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a unique structure with multiple layers and components to ensure proper connectivity and adhesion between the semiconductor chip and the surrounding elements.
- The first structure contains the first semiconductor chip, a first conductive pad, and a second conductive pad.
- A bump connects the first and second conductive pads.
- Two adhesive layers surround the bump and the side walls of the conductive pads, with the second adhesive layer made of a different material than the first adhesive layer.
- The horizontal width of the first adhesive layer is smaller than that of the second adhesive layer.
Potential Applications
This technology could be applied in various semiconductor devices and electronic components where secure and reliable connections between different elements are crucial.
Problems Solved
This innovation addresses the challenge of ensuring proper adhesion and connectivity in semiconductor packages, which is essential for the overall performance and reliability of electronic devices.
Benefits
The use of multiple adhesive layers with different materials helps enhance the bonding strength and stability of the semiconductor package, leading to improved durability and performance.
Potential Commercial Applications
This technology could be valuable in the manufacturing of advanced electronic devices such as smartphones, tablets, computers, and other consumer electronics.
Possible Prior Art
Prior art related to semiconductor packaging and adhesive bonding techniques may exist, but specific examples are not provided in the abstract.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods in terms of cost-effectiveness and efficiency?
This article does not provide information on the cost implications or efficiency gains of this technology compared to existing semiconductor packaging methods.
What are the environmental implications of using multiple adhesive layers with different materials in semiconductor packaging?
The abstract does not address the potential environmental impact of using multiple adhesive layers with different materials in semiconductor packaging.
Original Abstract Submitted
A semiconductor package includes a first structure, a first semiconductor chip on the first structure, a first conductive pad on the first structure between the first structure and the first semiconductor chip, a second conductive pad on a lower surface of the first semiconductor chip and vertically overlapping the first conductive pad, a bump connecting the first conductive pad and the second conductive pad, a first adhesive layer surrounding at least a part of side walls of the bump and side walls of the first conductive pad, and a second adhesive layer surrounding at least a part of the side walls of the bump and side walls of the second conductive pad, the second adhesive layer including a material different from the first adhesive layer, wherein a horizontal width of the first adhesive layer is smaller than a horizontal width of the second adhesive layer.
