18334099. SEMICONDUCTOR DEVICES simplified abstract (Samsung Electronics Co., Ltd.)

SEMICONDUCTOR DEVICES

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Junggun You of Suwon-si (KR)

Gigwan Park of Suwon-si (KR)

SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18334099 titled 'SEMICONDUCTOR DEVICES

Simplified Explanation

The semiconductor device described in the abstract includes active fins, isolation patterns, gate structures, and source/drain layers on a substrate. Here are the key points of the patent:

• The device has first and second active fins on different regions of the substrate.
• An isolation pattern separates the active fins and is located on the boundary between the regions.
• First and second gate structures are on the active fins and isolation patterns.
• First and second source/drain layers are adjacent to the gate structures on the active fins.
• The width of the first gate structure overlapping the first active fin is greater than that of the second gate structure overlapping the second active fin.

Potential applications of this technology:

• Advanced semiconductor devices
• High-performance integrated circuits
• Power-efficient electronics

Problems solved by this technology:

• Improved performance and efficiency of semiconductor devices
• Enhanced control over the flow of electrical current
• Reduction of leakage currents in electronic components

Benefits of this technology:

• Higher speed and performance of electronic devices
• Lower power consumption and energy efficiency
• Enhanced reliability and longevity of semiconductor components

Original Abstract Submitted

A semiconductor device includes first and second active fins on first and second regions of a substrate, an isolation pattern on a boundary between the first and second regions and portions of the first and second regions adjacent thereto and separating the first and second active fins, a first gate structure on the first active fin and the isolation pattern on the first region, a second gate structure on the second active fin and the isolation pattern on the second region, a first source/drain layer on the first active fin adjacent to the first gate structure, and a second source/drain layer on the second active fin adjacent to the second gate structure. A width of a portion of the first gate structure overlapping the first active fin is greater than that of a portion of the second gate structure overlapping the second active fin.