18331223. EQUALIZER FOR REMOVING INTER SYMBOL INTERFERENCE OF DATA SIGNAL BY INCREASING PULSE WIDTHS OF LOGIC LOW LEVEL AND LOGIC HIGH LEVEL OF DATA SIGNAL simplified abstract (Samsung Electronics Co., Ltd.)
EQUALIZER FOR REMOVING INTER SYMBOL INTERFERENCE OF DATA SIGNAL BY INCREASING PULSE WIDTHS OF LOGIC LOW LEVEL AND LOGIC HIGH LEVEL OF DATA SIGNAL
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EQUALIZER FOR REMOVING INTER SYMBOL INTERFERENCE OF DATA SIGNAL BY INCREASING PULSE WIDTHS OF LOGIC LOW LEVEL AND LOGIC HIGH LEVEL OF DATA SIGNAL - A simplified explanation of the abstract
This abstract first appeared for US patent application 18331223 titled 'EQUALIZER FOR REMOVING INTER SYMBOL INTERFERENCE OF DATA SIGNAL BY INCREASING PULSE WIDTHS OF LOGIC LOW LEVEL AND LOGIC HIGH LEVEL OF DATA SIGNAL
Simplified Explanation
The patent application describes an equalizer that includes pulse width controllers, samplers, and a multiplexer to process data signals.
- The first pulse width controller increases the pulse width of a data signal with a first logic level.
- The second pulse width controller increases the pulse width of the data signal with a second logic level.
- The first sampler generates a sampled signal by sampling the first signal.
- The second sampler generates a sampled signal by sampling the second signal.
- The multiplexer outputs either the first sampled signal or the second sampled signal based on the value of a previous data bit.
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- Potential Applications
- Signal processing in communication systems
- Data transmission in digital circuits
- Audio equalization in sound systems
- Problems Solved
- Improving signal quality by adjusting pulse widths
- Enhancing data transmission efficiency
- Providing flexibility in signal processing
- Benefits
- Increased accuracy in data signal processing
- Improved signal integrity
- Enhanced performance in communication systems
Original Abstract Submitted
An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.
