18329045. MEMORY DEVICE AND OPERATING METHOD THEREOF simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE AND OPERATING METHOD THEREOF
Organization Name
Inventor(s)
MEMORY DEVICE AND OPERATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18329045 titled 'MEMORY DEVICE AND OPERATING METHOD THEREOF
The memory device described in the patent application consists of multiple memory banks divided by multiple channels, including a first channel and a second channel. It also includes a channel-level processing element (PE) that can perform in-memory computations using data from different memory banks.
- The memory device has a plurality of memory banks divided by multiple channels.
- It includes a channel-level processing element (PE) that can generate in-memory computation results.
- The PE performs operations using partial results from memory banks in different channels.
Potential Applications:
- High-performance computing systems
- Data centers
- Artificial intelligence and machine learning applications
Problems Solved:
- Improving memory access speeds
- Enhancing computational efficiency
- Reducing data transfer bottlenecks
Benefits:
- Faster data processing
- Lower power consumption
- Improved overall system performance
Commercial Applications:
- High-speed data processing systems
- Cloud computing infrastructure
- Advanced scientific research facilities
Prior Art: There may be existing patents or technologies related to in-memory computation or memory processing elements in high-performance computing systems.
Frequently Updated Research: Stay updated on advancements in memory devices, in-memory computation techniques, and channel-level processing elements for improved performance and efficiency.
Questions about Memory Device with Channel-Level Processing Element: 1. How does the channel-level processing element improve computational efficiency in memory devices? 2. What are the potential challenges in implementing in-memory computation in memory devices with multiple channels?
Original Abstract Submitted
A memory device includes: a plurality of memory banks divided by a plurality of channels comprising a first channel and a second channel; and a channel-level processing element (PE) configured to generate an in-memory computation result by performing an operation using a first partial result generated based on data stored in a memory bank of the first channel among the plurality of memory banks and a second partial result generated based on data stored in a memory bank of the second channel among the plurality of memory banks.
