18323942. LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES simplified abstract (QUALCOMM Incorporated)

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LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES

Organization Name

QUALCOMM Incorporated

Inventor(s)

Sameer Wadhwa of San Diego CA (US)

Lennart Karl-Axel Mathe of San Diego CA (US)

LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18323942 titled 'LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES

Simplified Explanation

The patent application describes a low-power phase interpolator circuit that includes a phase generator, phase rotator circuit, frequency doubler circuit, and quadrature clock generation circuit.

  • The phase generator receives an input clock signal and generates multiple intermediate clock signals with different phase shifts.
  • The phase rotator circuit outputs phase-adjusted clock signals within a range bounded by phases of two intermediate clock signals.
  • The frequency doubler circuit receives the phase-adjusted clock signals and outputs two frequency-doubled clock signals with a 180° phase difference.
  • The quadrature clock generation circuit receives the frequency-doubled clock signals and provides four output signals, including in-phase and quadrature versions of the two frequency-doubled clock signals.

Potential applications of this technology:

  • Communication systems
  • Signal processing applications
  • Radar systems
  • Wireless networks

Problems solved by this technology:

  • Efficient generation of multiple clock signals with different phases
  • Low-power consumption
  • Precise phase adjustment capabilities

Benefits of this technology:

  • Reduced power consumption
  • Improved signal processing accuracy
  • Enhanced performance in communication systems
  • Versatile applications in various industries


Original Abstract Submitted

A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

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