18311696. POWER ON RESET (POR) CIRCUIT simplified abstract (NXP B.V.)
Contents
POWER ON RESET (POR) CIRCUIT
Organization Name
Inventor(s)
Sapna Sharma of Bangalore (IN)
Sanjay Kumar Wadhwa of Noida (IN)
POWER ON RESET (POR) CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18311696 titled 'POWER ON RESET (POR) CIRCUIT
The patent application describes a power-on reset (POR) circuit that includes a delay circuit to control the timing of signals sent to logic circuits after receiving a power supply voltage.
- The delay circuit outputs a first signal to the logic circuits before a delay time, and a second signal after the delay time.
- Components of the delay circuit include a voltage drop device, a switching device with on-resistance, and a capacitance device.
- The on-resistance of the switching device and the capacitance of the capacitance device determine the delay time.
Potential Applications: - Embedded systems - Microcontrollers - IoT devices
Problems Solved: - Ensures proper initialization of logic circuits after power-up - Prevents glitches or errors in system operation
Benefits: - Reliable power-on reset functionality - Improved system stability - Cost-effective implementation
Commercial Applications: Title: Power-on Reset Circuits for Embedded Systems This technology can be used in various electronic devices, such as microcontrollers and IoT devices, to ensure reliable power-on reset functionality, improving overall system stability and performance. The cost-effective implementation makes it a valuable addition to embedded systems.
Questions about Power-on Reset Circuits: 1. How does the delay circuit in a POR circuit contribute to the overall functionality of the system?
- The delay circuit controls the timing of signals sent to logic circuits, ensuring proper initialization after power-up.
2. What are the key components of a POR circuit and how do they work together to achieve a reliable power-on reset function?
- The voltage drop device, switching device, and capacitance device in the delay circuit work together to set the delay time and ensure a stable power-on reset operation.
Original Abstract Submitted
One example discloses a power on reset (POR) circuit, including: an input configured to receive a power supply voltage; a delay circuit configured to output a first signal to a set of logic circuits prior to a delay time; wherein the delay circuit is configured to output a second signal to the set of logic circuits after the delay time; wherein the delay circuit includes a voltage drop device coupled to receive the power supply voltage, a switching device having an on-resistance and coupled to the voltage drop device, and a capacitance device having a capacitance and coupled to the switching device; and wherein the on-resistance of the switching device and the capacitance of the capacitance device together are configured to set the delay time.
