18302401. LAYOUT METHOD OF SEMICONDUCTOR, INSPECTION METHOD OF WAFER, MANUFACTURING METHOD OF THE WAFER AND MANUFACTURING METHOD OF MULTI-CHIP PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)

From WikiPatents
Jump to navigation Jump to search

LAYOUT METHOD OF SEMICONDUCTOR, INSPECTION METHOD OF WAFER, MANUFACTURING METHOD OF THE WAFER AND MANUFACTURING METHOD OF MULTI-CHIP PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Sumin Park of Suwon-si (KR)

Taeseong Kim of Suwon-si (KR)

Jaehyung Park of Suwon-si (KR)

Kyuha Lee of Suwon-si (KR)

Yeojin Lee of Suwon-si (KR)

Kwangjin Moon of Suwon-si (KR)

Hojin Lee of Suwon-si (KR)

LAYOUT METHOD OF SEMICONDUCTOR, INSPECTION METHOD OF WAFER, MANUFACTURING METHOD OF THE WAFER AND MANUFACTURING METHOD OF MULTI-CHIP PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18302401 titled 'LAYOUT METHOD OF SEMICONDUCTOR, INSPECTION METHOD OF WAFER, MANUFACTURING METHOD OF THE WAFER AND MANUFACTURING METHOD OF MULTI-CHIP PACKAGE

Simplified Explanation

The abstract describes a manufacturing method for a wafer that involves measuring the surface roughness and step difference values of metal lines in a test region using an atomic force microscope (AFM).

  • The method includes preparing a wafer with a semiconductor chip region and a test region.
  • Measuring a measurement region in the test region with an AFM, which contains metal lines with constant line width and pitch.
  • Determining the surface roughness value of the test region based on the AFM measurements.
  • Determining the step difference value of the metal lines in the test region based on the surface roughness value.
  • Determining the step difference value of bonding pads in the semiconductor chip region based on the step difference value of the metal lines.

---

      1. Potential Applications
  • Quality control in semiconductor manufacturing.
  • Improving the reliability and performance of semiconductor devices.
      1. Problems Solved
  • Ensuring uniformity and accuracy in the fabrication of metal lines on wafers.
  • Facilitating the evaluation of bonding pads in semiconductor chips.
      1. Benefits
  • Enhanced quality control in wafer manufacturing.
  • Improved performance and reliability of semiconductor devices.
  • Efficient evaluation of bonding pads for better overall functionality.


Original Abstract Submitted

In a manufacturing method of a wafer, the method including: an operation of preparing a wafer including a semiconductor chip region and a test region, measuring a measurement region included in the test region with an atomic force microscope (AFM), the measurement region including a plurality of metal lines having a constant line width and a constant pitch; determining a surface roughness value of the test region based on a result of the measuring of the measurement region; determining a step difference value of the metal lines of the test region based on the surface roughness value; and determining a step difference value of bonding pads in the semiconductor chip region based on the step difference value of the metal lines.