18299265. WAFER-LEVEL MULTI-DEVICE TESTER AND SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
WAFER-LEVEL MULTI-DEVICE TESTER AND SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Seongkwan Lee of Suwon-si (KR)
WAFER-LEVEL MULTI-DEVICE TESTER AND SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18299265 titled 'WAFER-LEVEL MULTI-DEVICE TESTER AND SYSTEM INCLUDING THE SAME
Simplified Explanation
The patent application describes a tester designed to test multiple devices under test (DUTs) efficiently. It includes signal analysis circuits to analyze signals from the DUTs and signal processing units to process these signals. A switch array connects the analysis circuits to the processing units, allowing for flexible connections between them.
- Tester for analyzing signals from multiple devices under test (DUTs)
- Signal analysis circuits to analyze signals from DUTs
- Signal processing units to process signals analyzed by the analysis circuits
- Switch array to connect analysis circuits with processing units
- Flexibility in connecting different analysis circuits with processing units
- Efficient testing of multiple DUTs with fewer processing units
Potential Applications
- Electronic manufacturing
- Quality control testing
- Research and development labs
Problems Solved
- Efficient testing of multiple devices simultaneously
- Flexibility in connecting analysis and processing units
- Streamlining the testing process
Benefits
- Faster testing of multiple devices
- Cost-effective solution for testing
- Improved accuracy in signal analysis
- Flexibility in test configurations
Original Abstract Submitted
A tester, which is adapted to test a device under test (DUT), includes a first plurality of signal analysis circuits configured to analyze signals generated by a plurality of DUTs, and a second plurality of signal processing units configured to process the signals analyzed by the first plurality of signal analysis circuits. A switch array is provided, which is electrically coupled between the first plurality of signal analysis circuits and the second plurality of signal processing units. The switch array is configured to electrically connect selected ones of the first plurality of signal analysis circuits with corresponding ones of the second plurality of signal processing units. The number of signal processing units within the second plurality may be less than a maximum number of DUTs that can be connected to the first plurality of signal analysis circuits when the tester is testing a plurality of the DUTs.
