18243421. DEBUG FOR MULTI-THREADED PROCESSING simplified abstract (Texas Instruments Incorporated)

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DEBUG FOR MULTI-THREADED PROCESSING

Organization Name

Texas Instruments Incorporated

Inventor(s)

NIRAJ Nandan of PLANO TX (US)

HETUL Sanghvi of MURPHY TX (US)

MIHIR Mody of BANGALORE (IN)

GARY Cooper of OAKMONT PA (US)

ANTHONY Lell of SAN ANTONIO TX (US)

DEBUG FOR MULTI-THREADED PROCESSING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18243421 titled 'DEBUG FOR MULTI-THREADED PROCESSING

Simplified Explanation

The abstract describes a system for implementing debugging in a multi-threaded processor. The system includes a hardware thread scheduler, multiple schedulers for processing instructions, a debug control, and hardware accelerators.

  • The system includes a hardware thread scheduler that schedules the processing of data.
  • Multiple schedulers are present, each responsible for scheduling a specific pipeline for processing instructions.
  • A debug control is included to control the schedulers, allowing them to halt, step, or resume the processing of data for debugging purposes.
  • The system also includes multiple hardware accelerators that execute instructions for a given pipeline based on a schedule provided by a scheduler.
  • Each hardware accelerator is connected to at least one scheduler and a shared memory.

Potential Applications

  • Debugging multi-threaded processors.
  • Improving the efficiency and performance of multi-threaded processors.

Problems Solved

  • Debugging complex multi-threaded processors can be challenging. This system provides a solution by allowing for the control and monitoring of individual pipelines for debugging purposes.
  • The system also helps in improving the overall efficiency and performance of multi-threaded processors by utilizing hardware accelerators and optimized scheduling.

Benefits

  • Enhanced debugging capabilities for multi-threaded processors.
  • Improved efficiency and performance of multi-threaded processors.
  • Better control and monitoring of individual pipelines for debugging purposes.


Original Abstract Submitted

A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

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