18238269. MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES simplified abstract (Micron Technology, Inc.)

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES

Organization Name

Micron Technology, Inc.

Inventor(s)

Durai Vishak Nirmal Ramaswamy of Boise ID (US)

Karthik Sarpatwari of Boise ID (US)

Kamal M. Karda of Boise ID (US)

Pankaj Sharma of Boise ID (US)

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18238269 titled 'MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES

Simplified Explanation

• • Explanation:**

The patent application describes an apparatus for memory cells, which includes data lines, dielectric structures, transistors, and charge storage structures.

• The apparatus includes a first data line and a second data line separated by a dielectric structure.
• A memory cell is formed over the data lines, consisting of two transistors and a charge storage structure.
• The first transistor has a channel region coupled to the first data line, while the charge storage structure is separated from this region.
• The second transistor has a channel region coupled to the second data line, with the charge storage structure formed over and coupled to this region.
• A dielectric structure is present between the first channel region and the second channel region/charge storage structure.

• • Potential Applications:**
• Memory devices
• Solid-state drives
• Embedded memory in electronic devices

• • Problems Solved:**
• Increased data storage capacity
• Improved data retention and retrieval
• Enhanced memory cell performance

• • Benefits:**
• Higher memory density
• Faster data access speeds
• More reliable data storage

Original Abstract Submitted

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line; a second data line adjacent the first data line and separated from the first data line by a first dielectric structure; and a memory cell formed over the first and second data lines. The memory cell includes a first transistor including a first channel region formed over and coupled to the first data line, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over and coupled to the second data line, wherein the charge storage structure is formed over and coupled to the second channel region; and a second dielectric structure between the first channel region and each of the second channel region and the charge storage structure.