18236579. MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK simplified abstract (Micron Technology, Inc.)
Contents
MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK
Organization Name
Inventor(s)
Russell Allen Benson of Boise ID (US)
Shivani Srivastava of Boise ID (US)
Raghunath Singanamalla of Boise ID (US)
MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK - A simplified explanation of the abstract
This abstract first appeared for US patent application 18236579 titled 'MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK
Simplified Explanation
The patent application describes an apparatus with a memory device that has digit line contacts in a dielectric, with metal digit lines connected to some of the digit line contacts through a metal barrier. The metal digit lines also serve as contact metal to a transistor in the periphery of the memory array region, with multiple barrier metals on polysilicon on the transistor connecting the metal contact.
- Memory device with digit line contacts in dielectric
- Metal digit lines connected to digit line contacts through metal barrier
- Metal digit lines used as contact metal to transistor in periphery
- Multiple barrier metals on polysilicon on transistor connecting metal contact
- Potential Applications
- Semiconductor manufacturing - Memory devices - Integrated circuits
- Problems Solved
- Efficient integration flow for metallization in periphery devices to memory array - Separate barrier metal formation between memory array and periphery - Clearing of barrier metals from memory array region before forming main conductor
- Benefits
- Improved efficiency in semiconductor manufacturing - Enhanced performance of memory devices - Simplified integration flow for metallization in integrated circuits
Original Abstract Submitted
A variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. Material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. An integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. Barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.
