18235643. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
HYEONJEONG Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18235643 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the patent application includes an interposer substrate, a chip stack with vertically stacked first semiconductor chips, a second semiconductor chip horizontally spaced apart from the chip stack, a molding layer surrounding the chip stack and the second semiconductor chip, a redistribution layer on the molding layer, and conductive posts connecting the interposer substrate to the redistribution layer.
- Interposer substrate
- Chip stack with vertically stacked first semiconductor chips
- Second semiconductor chip horizontally spaced apart from the chip stack
- Molding layer surrounding the chip stack and second semiconductor chip
- Redistribution layer on the molding layer
- Conductive posts connecting the interposer substrate to the redistribution layer
Potential Applications: - Advanced semiconductor packaging technology - High-density integrated circuits - Miniaturized electronic devices
Problems Solved: - Enhancing performance and efficiency of semiconductor packages - Increasing integration density in electronic devices
Benefits: - Improved signal transmission - Enhanced thermal management - Reduced footprint in electronic devices
Commercial Applications: - Consumer electronics - Telecommunications equipment - Automotive electronics
Questions about semiconductor packaging technology: 1. How does the vertical stacking of semiconductor chips benefit the overall performance of the package? 2. What are the key advantages of using conductive posts to connect the interposer substrate to the redistribution layer?
Original Abstract Submitted
Disclosed is a semiconductor package comprising an interposer substrate, a chip stack on the interposer substrate and including first semiconductor chips that are vertically stacked, a second semiconductor chip on the interposer substrate and horizontally spaced apart from the chip stack, a molding layer on the interposer substrate and surrounding the chip stack and the second semiconductor chip, a redistribution layer on the molding layer, and a plurality of conductive posts that vertically penetrate the molding layer and connect the interposer substrate to the redistribution layer.
