18235033. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
DONGHYEON Jang of SUWON-SI (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18235033 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a lower redistribution wiring layer with stacked first redistribution wirings, a semiconductor chip connected to the first redistribution wirings, a sealing member covering the chip, through vias penetrating the sealing member and connected to the first redistribution wirings, and an upper redistribution wiring layer with second redistribution wirings connected to the through vias. Each first redistribution wiring includes a barrier layer pattern, a seed layer pattern, and a plating pattern stacked sequentially, with the barrier layer pattern extending laterally beyond the seed layer pattern in plan view.
- Lower redistribution wiring layer with stacked first redistribution wirings
- Semiconductor chip electrically connected to first redistribution wirings
- Sealing member covering semiconductor chip
- Through vias penetrating sealing member and connected to first redistribution wirings
- Upper redistribution wiring layer with second redistribution wirings connected to through vias
Potential Applications
This technology can be applied in various semiconductor packaging applications where high-density wiring and electrical connections are required.
Problems Solved
This technology solves the problem of achieving efficient and reliable electrical connections in semiconductor packages with multiple wiring layers.
Benefits
The benefits of this technology include improved electrical performance, increased packaging density, and enhanced reliability of semiconductor devices.
Potential Commercial Applications
Potential commercial applications of this technology include advanced microprocessors, memory modules, and other high-performance semiconductor devices.
Possible Prior Art
One possible prior art for this technology could be the use of multi-layer wiring structures in semiconductor packages to improve electrical connectivity and performance.
Unanswered Questions
How does this technology compare to existing semiconductor packaging solutions in terms of cost-effectiveness?
This article does not provide information on the cost-effectiveness of this technology compared to existing solutions. Further research and analysis would be needed to determine the cost implications of implementing this technology in semiconductor packaging.
What are the environmental implications of using this technology in semiconductor manufacturing processes?
The environmental impact of using this technology in semiconductor manufacturing processes is not addressed in this article. Additional studies would be required to assess the environmental footprint of implementing this technology and its potential sustainability benefits.
Original Abstract Submitted
A semiconductor package includes a lower redistribution wiring layer having first redistribution wirings stacked in at least two layers, a semiconductor chip disposed on the lower redistribution wiring layer and electrically connected to the first redistribution wirings, a sealing member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of through vias penetrating the sealing member and electrically connected to the first redistribution wirings, and an upper redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of through vias. Each of the first redistribution wirings includes a barrier layer pattern, a seed layer pattern and a plating pattern sequentially stacked. From a plan view, a sidewall of the barrier layer pattern extends laterally beyond a sidewall of the seed layer pattern.
