18233433. MULTIPLE MEMORY BLOCK ERASE OPERATION simplified abstract (Micron Technology, Inc.)
Contents
MULTIPLE MEMORY BLOCK ERASE OPERATION
Organization Name
Inventor(s)
MULTIPLE MEMORY BLOCK ERASE OPERATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18233433 titled 'MULTIPLE MEMORY BLOCK ERASE OPERATION
Simplified Explanation
The patent application describes a memory sub-system that can initiate an erase operation to erase memory cells in two different memory blocks concurrently.
- Memory sub-system initiates erase operation for first set of memory cells in first memory block and second set of memory cells in second memory block simultaneously.
- One or more erase pulses are applied to both sets of memory cells at the same time.
- Erase verify sub-operations are performed to confirm erasure of each memory block individually.
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- Potential Applications
- Data storage devices
- Solid-state drives
- Flash memory
- Problems Solved
- Efficient erasure of memory blocks
- Simultaneous erasure of multiple memory blocks
- Reduced erase operation time
- Benefits
- Faster erase operations
- Improved memory management
- Enhanced data security and privacy
Original Abstract Submitted
A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.
