18232810. PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS simplified abstract (Intel Corporation)

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PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS

Organization Name

Intel Corporation

Inventor(s)

Vedvyas Shanbhogue of Austin TX (US)

Jason W. Brandt of Austin TX (US)

Ravi L. Sahita of Portland OR (US)

Barry E. Huntley of Hillsboro OR (US)

Baiju V. Patel of Portland OR (US)

Deepak K. Gupta of Portland OR (US)

PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232810 titled 'PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS

Simplified Explanation

The abstract describes a processor that implements techniques to protect stacks during transitions between different privilege levels. The processor includes multiple registers and a processor core. Each register is associated with a privilege level and stores data used during privilege level transitions.

  • The processor receives an indicator to change the privilege level of an active application.
  • Based on the new privilege level, the processor selects a shadow stack pointer (SSP) stored in a register associated with that privilege level.
  • The SSP is used to identify a shadow stack for the processor to use at the new privilege level.

Potential Applications

  • This technology can be applied in processors used in operating systems, where different applications or processes may run at different privilege levels.
  • It can be used in systems that require secure and efficient context switching between privilege levels.

Problems Solved

  • Protecting stacks during transitions between privilege levels can help prevent unauthorized access or modification of data.
  • Ensuring the integrity and security of data during privilege level transitions is crucial for system stability and security.

Benefits

  • The use of shadow stacks provides an additional layer of protection for sensitive data during privilege level transitions.
  • By associating registers with specific privilege levels, the processor can efficiently manage and switch between different privilege levels.
  • The techniques implemented in this processor extension help enhance the security and reliability of systems that require privilege level transitions.


Original Abstract Submitted

A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

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