18228209. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Hyeon Jeong Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18228209 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract includes an interposer placed on a substrate, with a recess on the interposer's upper surface housing a connection structure. A first post on the interposer is connected to the interposer, while a second post on the connection structure is connected to the connection structure. A first lower semiconductor chip is positioned between the first and second posts, resting on both the interposer and the connection structure. The first lower semiconductor chip is linked to the second post through the connection structure, and a first upper semiconductor chip is placed on top of the first lower semiconductor chip, connected to it through the second post and the connection structure.
- Interposer with recess and connection structure
- First and second posts for electrical connections
- Placement of first lower semiconductor chip on interposer and connection structure
- Connection of first lower and upper semiconductor chips through posts and connection structure
Potential Applications: - Advanced semiconductor packaging technology - High-density integrated circuits - Improved electrical connections in semiconductor devices
Problems Solved: - Enhanced electrical connectivity in semiconductor packages - Efficient use of space in semiconductor packaging
Benefits: - Increased performance and reliability of semiconductor devices - Compact design for space-saving applications
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for High-Performance Electronics This technology can be utilized in various industries such as telecommunications, automotive, consumer electronics, and aerospace for high-performance electronic devices requiring compact and reliable semiconductor packaging solutions.
Questions about the technology: 1. How does the placement of the first lower semiconductor chip on both the interposer and connection structure improve electrical connections? 2. What are the potential advantages of using an interposer with a recess and connection structure in semiconductor packaging?
Original Abstract Submitted
A semiconductor package an interposer disposed on a substrate, a recess recessed from an upper surface of the interposer, a connection structure disposed inside the recess, a first post disposed on the upper surface of the interposer and electrically connected to the interposer, a second post disposed on an upper surface of the connection structure and electrically connected to the connection structure, a first lower semiconductor chip disposed between the first and second posts and disposed on the upper surface of the interposer and the upper surface of the connection structure. The first lower semiconductor chip is electrically connected to the second post through the connection structure, and a first upper semiconductor chip is disposed on an upper surface of the first lower semiconductor chip. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the second post and the connection structure.
