18227348. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
KYOUNG LIM Suk of Suwon-si (KR)
HYEONJEONG Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18227348 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The semiconductor package described in the patent application comprises multiple layers and components, including semiconductor chips, molding layers, redistribution substrates, and posts. The package is designed to provide efficient electrical connections and protection for the semiconductor chips.
- Lower semiconductor chip on a first redistribution substrate with a through via
- Lower molding layer surrounding the lower semiconductor chip
- Lower post laterally spaced apart from the lower semiconductor chip
- Upper semiconductor chip on the lower semiconductor chip connected to the through via
- Upper molding layer surrounding the upper semiconductor chip
- Upper post laterally spaced apart from the upper semiconductor chip
- Second redistribution substrate on the upper molding layer connected to the upper post
- Top surface of the lower molding layer is higher than the top surface of the lower semiconductor chip
Potential Applications
The technology described in this patent application could be applied in various industries, including electronics, telecommunications, automotive, and aerospace.
Problems Solved
This technology solves the problem of efficiently connecting and protecting semiconductor chips in a compact and reliable package.
Benefits
The benefits of this technology include improved performance, reliability, and durability of semiconductor packages, leading to enhanced overall product quality.
Potential Commercial Applications
Potential commercial applications of this technology include advanced electronic devices, communication systems, automotive electronics, and aerospace components.
Possible Prior Art
One possible prior art could be the use of multi-layer semiconductor packages with through vias and redistribution substrates in the semiconductor industry.
Unanswered Questions
1. How does the design of this semiconductor package compare to existing packaging solutions in terms of size and performance? 2. Are there any specific industries or applications where this technology would be most beneficial compared to traditional packaging methods?
Original Abstract Submitted
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.
