18218886. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Youngdeuk Kim of Suwon-si (KR)
Heejung Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18218886 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a lower chip, a chip structure with stacked semiconductor chips, and an adhesive film. The semiconductor chips consist of first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other. The first bonding chips include a first bonding lower chip with a first bonding upper pad, and a first bonding upper chip on top of the first bonding lower chip with a first bonding lower pad. The second bonding chips include a second bonding lower chip with a second bonding upper insulating layer and a second bonding upper pad, and a second bonding upper chip on top of the second bonding lower chip with a second bonding lower insulating layer and a second bonding lower pad. The adhesive film surrounds the side surfaces of the bumps, fills the region between the first bonding lower and upper chips, and protrudes from the region.
- The semiconductor package includes stacked semiconductor chips bonded to each other using bumps and adhesive film.
- The first bonding chips consist of a lower chip and an upper chip, while the second bonding chips consist of a lower chip with an insulating layer and an upper chip.
- The adhesive film surrounds the bumps and fills the gap between the first bonding chips.
- The adhesive film protrudes from the region between the first bonding chips.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- Integrated circuits for automotive electronics, aerospace systems, and industrial equipment.
Problems solved by this technology:
- Improved bonding and stacking of semiconductor chips, leading to increased performance and reliability.
- Enhanced thermal management and electrical connectivity in semiconductor packages.
Benefits of this technology:
- Higher integration density and miniaturization of electronic devices.
- Improved thermal dissipation and electrical performance.
- Enhanced reliability and durability of semiconductor packages.
Original Abstract Submitted
A semiconductor package including: a lower chip; a chip structure including stacked semiconductor chips; and an adhesive film, the semiconductor chips include first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other, the first bonding chips include: a first bonding lower chip including a first bonding upper pad; and a first bonding upper chip on the first bonding lower chip and including a first bonding lower pad, the second bonding chips include: a second bonding lower chip including a second bonding upper insulating layer and a second bonding upper pad; and a second bonding upper chip on the second bonding lower chip and including a second bonding lower insulating layer, and a second bonding lower pad, and the adhesive film surrounds side surfaces of the bumps, fills a region between the first bonding lower and upper chips, and protrudes from the region.
