18203877. TECHNIQUES TO MANUFACTURE FERROELECTRIC MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
TECHNIQUES TO MANUFACTURE FERROELECTRIC MEMORY DEVICES
Organization Name
Inventor(s)
Giorgio Servalli of Fara Gera d'Adda (IT)
Marcello Mariani of Milano (IT)
Agostino Pirovano of Milano (IT)
TECHNIQUES TO MANUFACTURE FERROELECTRIC MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18203877 titled 'TECHNIQUES TO MANUFACTURE FERROELECTRIC MEMORY DEVICES
Simplified Explanation
The abstract describes methods, systems, and devices for manufacturing ferroelectric memory devices using a self-aligned manufacturing technique. This technique involves forming a continuous layer of dielectric material over an assembly that includes an array of transistors and contacts. Cavities are then etched into the dielectric material, exposing the contacts. Bottom electrodes are formed on the sidewalls of each cavity by depositing and etching a layer of electrode material.
- A continuous layer of dielectric material is formed over an assembly containing transistors and contacts.
- Cavities are etched into the dielectric material, exposing the contacts.
- Bottom electrodes are formed on the sidewalls of each cavity by depositing and etching a layer of electrode material.
Potential Applications
- Manufacturing ferroelectric memory devices
- Memory arrays
Problems Solved
- Simplified and efficient manufacturing of ferroelectric memory devices
- Self-aligned manufacturing technique reduces the complexity of the manufacturing process
Benefits
- Improved manufacturing efficiency
- Enhanced memory device performance
- Cost-effective production
Original Abstract Submitted
Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.
