18203754. MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT
Organization Name
Inventor(s)
Daeseok Byeon of Suwon-si (KR)
MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18203754 titled 'MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT
Simplified Explanation
The abstract describes a memory device with a memory cell array and a page buffer circuit to reduce coupling problems caused by low capacitance of the sensing node.
- Memory device with memory cell array and page buffer circuit
- Page buffer units connected to memory cells through bit lines
- Sensing node connected to each buffer circuit's bit line
- Page buffer units connected to sensing nodes, each including at least one transistor
- Auxiliary wires near sensing node to reduce coupling problems
Potential Applications
The technology described in this patent application could be applied in various memory devices such as solid-state drives, computer memory modules, and mobile devices.
Problems Solved
The innovation addresses coupling problems caused by the low capacitance of sensing nodes in memory devices, improving data reliability and performance.
Benefits
- Enhanced data reliability - Improved memory device performance - Reduced coupling issues - Increased efficiency in memory operations
Potential Commercial Applications
The technology could be utilized in the production of high-performance memory devices for consumer electronics, data centers, and other computing applications.
Possible Prior Art
One possible prior art could be memory devices with sensing nodes but lacking the use of auxiliary wires to reduce coupling problems caused by low capacitance.
What is the manufacturing cost of implementing this technology in memory devices?
Implementing this technology may increase manufacturing costs due to the additional components required, such as the auxiliary wires and transistors in the page buffer units.
How does this technology compare to existing solutions in terms of data transfer speed?
This technology may improve data transfer speed by reducing coupling problems and enhancing the efficiency of memory operations, potentially outperforming existing solutions in certain scenarios.
Original Abstract Submitted
A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.
