18194511. MEMORY, CONTROLLER AND COMPUTING SYSTEM CAPABLE OF REDUCING POWER CONSUMPTION simplified abstract (SK hynix Inc.)

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MEMORY, CONTROLLER AND COMPUTING SYSTEM CAPABLE OF REDUCING POWER CONSUMPTION

Organization Name

SK hynix Inc.

Inventor(s)

Jin Ho Baek of Icheon-si (KR)

Young Pyo Joo of Icheon-si (KR)

MEMORY, CONTROLLER AND COMPUTING SYSTEM CAPABLE OF REDUCING POWER CONSUMPTION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18194511 titled 'MEMORY, CONTROLLER AND COMPUTING SYSTEM CAPABLE OF REDUCING POWER CONSUMPTION

Simplified Explanation

The computing system described in the patent application is designed to store and manage different types of data in memory efficiently. The system divides the data into parts, generates parity information for one part, and stores it in memory with different refresh intervals based on the type of data.

  • The system stores a first type of data and a second type of data in memory.
  • It divides the first type of data into a first part and a second part.
  • Parity information is generated for the first part and stored in memory.
  • The refresh interval for the region of memory where the first type of data is stored is larger than the refresh interval for the region where the second type of data is stored.

Potential Applications

This technology could be applied in:

  • Data storage systems
  • Error correction systems
  • Memory management systems

Problems Solved

This technology addresses issues such as:

  • Efficient data storage
  • Data integrity and reliability
  • Memory refresh optimization

Benefits

The benefits of this technology include:

  • Improved data management
  • Enhanced data protection
  • Optimal memory performance

Potential Commercial Applications

Optimized Memory Management for Data Integrity and Performance

Possible Prior Art

Prior art related to memory management systems and data storage techniques may exist, but specific examples are not provided in the patent application.

Unanswered Questions

How does the system determine the refresh intervals for different regions of memory?

The patent application does not detail the specific method or algorithm used to determine the refresh intervals for different regions of memory.

What impact does the different refresh intervals have on overall system performance?

The patent application does not discuss the potential performance implications of having varying refresh intervals for different regions of memory.


Original Abstract Submitted

A computing system comprises a memory and a controller, and the controller is configured to store a first type of data and a second type of data in the memory, to divide the first type of data into a first part and a second part, to generate parity information on the first part and to store the parity information in the memory, and a refresh interval of a region of the memory where the first type of data is stored is larger than a refresh interval of a region of the memory where the second type of data is stored.