18189599. DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME
Organization Name
Inventor(s)
Myoungbo Kwak of Suwon-si (KR)
Junghwan Choi of Suwon-si (KR)
DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18189599 titled 'DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME
Simplified Explanation
The abstract describes a digital phase-locked loop (PLL) system that consists of the following components:
- A digitally controlled oscillator (DCO) that can adjust its oscillation frequency based on a control signal.
- A divider that generates a feedback signal by dividing the frequency of the oscillation signal.
- A time-to-digital converter (TDC) that detects the phase difference between a reference signal and the feedback signal, producing an error signal proportional to the phase difference.
- A digital loop filter that generates the frequency control signal based on the error signal and the oscillation signal.
Potential Applications:
- Wireless communication systems
- Frequency synthesizers
- Clock and data recovery circuits
Problems Solved:
- Precise frequency and phase synchronization
- Reduction of phase noise and spurious signals
- Improved signal integrity and reliability in communication systems
Benefits:
- Enhanced performance and accuracy in frequency control
- Increased stability and robustness in signal processing
- Greater flexibility and adaptability in various applications
Original Abstract Submitted
A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
