18182066. METHOD OF 3D CANTILEVER CHANNEL FORMATION simplified abstract (Tokyo Electron Limited)
Contents
METHOD OF 3D CANTILEVER CHANNEL FORMATION
Organization Name
Inventor(s)
H. Jim Fulford of Marianna FL (US)
Mark I. Gardner of Cedar Creek TX (US)
METHOD OF 3D CANTILEVER CHANNEL FORMATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18182066 titled 'METHOD OF 3D CANTILEVER CHANNEL FORMATION
The method described in the patent application involves fabricating a semiconductor device by forming a patterned multilayered stack on a substrate, with sacrificial layers alternatingly stacked with channel layers.
- Cantilever supports are then formed on the substrate, each in contact with a respective opposing end of the patterned multilayered stack.
- Gate-all-around (GAA) structures are formed around each channel layer while the multilayered stack is supported by the cantilever supports.
- The cantilever supports are removed to expose end portions of each channel layer, allowing for the formation of source-drain (S-D) regions on the exposed end portions.
Potential Applications: - This technology can be applied in the manufacturing of advanced semiconductor devices with improved performance and efficiency. - It can be used in the production of high-density memory chips and processors for various electronic devices.
Problems Solved: - Enables the creation of more compact and efficient semiconductor devices. - Facilitates the formation of precise source-drain regions for enhanced device functionality.
Benefits: - Enhanced performance and efficiency of semiconductor devices. - Increased density and functionality of integrated circuits. - Improved reliability and longevity of electronic devices.
Commercial Applications: - The technology can be utilized in the production of smartphones, tablets, laptops, and other consumer electronics. - It can also be applied in the development of advanced computing systems and data storage devices.
Questions about the Technology: 1. How does the removal of cantilever supports impact the overall structure of the semiconductor device? 2. What are the specific advantages of using a gate-all-around (GAA) structure in this fabrication process?
Original Abstract Submitted
A method of fabricating a semiconductor device includes forming on a patterned multilayered stack including sacrificial layers alternatingly stacked with channel layers on a substrate, the patterned multilayered stack having opposing sidewalls and opposing ends. Cantilever supports are formed on the substrate, each cantilever support being in contact with a respective opposing end of the patterned multilayered stack. A gate-all-around (GAA) structure is formed around each channel layer while the opposing ends of the multilayered stack are supported by the cantilever supports. The cantilever supports are removed from the opposing ends of the patterned multilayered stack to expose end portions of each channel layer, and source-drain (S-D) regions are formed on the exposed end portions of each respective channel layer.
