18177704. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
Natsuki Sakaguchi of Chiyoda Tokyo (JP)
Takashi Maeda of Kamakura Kanagawa (JP)
Rieko Funatsuki of Yokohama Kanagawa (JP)
Hidehiro Shiga of Yokohama Kanagawa (JP)
SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18177704 titled 'SEMICONDUCTOR MEMORY DEVICE
Simplified Explanation
The control circuit of a semiconductor memory device performs a write operation on a memory cell transistor by first lowering the threshold voltage of the memory cell transistor, then performing a precharge operation, and finally a second pulse application operation.
- Lowering the threshold voltage of the memory cell transistor
- Precharge operation
- Second pulse application operation
- Potential Applications:**
- Memory devices - Semiconductor technology
- Problems Solved:**
- Efficient write operations on memory cell transistors - Improved performance of semiconductor memory devices
- Benefits:**
- Faster write operations - Enhanced memory cell transistor functionality
- Potential Commercial Applications:**
- Memory chip manufacturing - Semiconductor industry advancements
- Possible Prior Art:**
- Previous patents related to memory cell transistor write operations
- Unanswered Questions:**
- 1. How does this control circuit compare to existing memory device write operation methods?**
- The article does not provide a direct comparison to existing methods, leaving the reader to wonder about the specific advantages of this new approach.
- 2. Are there any limitations or drawbacks to using this control circuit in semiconductor memory devices?**
- The article does not address any potential limitations or drawbacks of implementing this control circuit, leaving room for further exploration of its practical implications.
Original Abstract Submitted
A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.
