18174186. SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
Organization Name
Inventor(s)
Gilyoung Kang of Suwon-si (KR)
SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18174186 titled 'SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
Simplified Explanation
The semiconductor memory device described in the patent application includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The ECC engine consists of a first latch and a second latch. The control logic circuit activates a test mode in the memory device when it receives a specific command. In the test mode, the ECC engine disconnects from the memory cell array, receives test data, stores it in the first latch, performs ECC decoding on the test data and a test parity data stored in the second latch when a read command is given, and provides a severity signal to an external device indicating whether there are any error bits in the test data and test parity data, and if so, whether they can be corrected.
- The semiconductor memory device has an on-die ECC engine that performs error correction on test data.
- The ECC engine includes a first latch and a second latch for storing test data and test parity data.
- The control logic circuit activates a test mode in response to a specific command.
- In the test mode, the ECC engine disconnects from the memory cell array and performs ECC decoding on the stored test data and test parity data.
- The severity signal provided by the ECC engine indicates the presence of error bits in the test data and test parity data and whether they can be corrected.
Potential applications of this technology:
- Memory testing and validation: The ability to perform ECC decoding on test data can be used to verify the integrity of memory cells and ensure error-free data storage.
- Fault diagnosis: The severity signal indicating the presence and correctability of error bits can help identify and locate faults in the memory system.
Problems solved by this technology:
- Error detection and correction: The ECC engine allows for the identification and correction of error bits in the stored data, improving the reliability of the memory device.
- Test data integrity: The ability to perform ECC decoding on test data ensures that the data used for testing and validation is accurate and reliable.
Benefits of this technology:
- Improved memory reliability: By detecting and correcting errors, the ECC engine enhances the overall reliability of the memory device.
- Efficient testing and validation: The on-die ECC engine eliminates the need for external error correction mechanisms, simplifying the testing and validation process.
- Fault localization: The severity signal provided by the ECC engine helps pinpoint the location of errors, facilitating faster fault diagnosis and repair.
Original Abstract Submitted
A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.
