18171074. Scan Flip Flop simplified abstract (Meta Platforms Technologies, LLC)
Contents
Scan Flip Flop
Organization Name
Meta Platforms Technologies, LLC
Inventor(s)
Saurabh Kumar of Portland OR (US)
Scan Flip Flop - A simplified explanation of the abstract
This abstract first appeared for US patent application 18171074 titled 'Scan Flip Flop
Simplified Explanation: The patent application describes a scan flip-flop that includes a multiplexer to select inputs, a master latch to latch selected data, a switch controlled by clock signals, and a slave latch to latch data from the master latch.
Key Features and Innovation:
- Multiplexer selects inputs for the flip-flop.
- Master latch latches selected data.
- Switch controlled by clock signals.
- Slave latch latches data from the master latch.
- Tri-state inverter in the slave latch supplies current to the multiplexer.
Potential Applications: The technology can be used in digital circuits, memory devices, and integrated circuits for efficient data storage and retrieval.
Problems Solved: The scan flip-flop addresses the need for reliable and efficient data storage and retrieval in digital systems.
Benefits:
- Improved data storage and retrieval efficiency.
- Enhanced reliability in digital circuits.
- Simplified design and operation of integrated circuits.
Commercial Applications: Potential commercial applications include semiconductor manufacturing, electronics industry, and computer hardware development.
Prior Art: Readers can explore prior patents related to flip-flop circuits, latch designs, and clock signal control mechanisms for further research.
Frequently Updated Research: Stay updated on advancements in digital circuit design, semiconductor technology, and integrated circuit innovations related to flip-flop circuits.
Questions about Scan Flip-Flop Technology: 1. How does the tri-state inverter in the slave latch contribute to the overall functionality of the scan flip-flop? 2. What are the key differences between this scan flip-flop design and traditional flip-flop circuits?
Original Abstract Submitted
A scan flip-flop comprising a multiplexer configured to select from a plurality of inputs of the flip-flop. The scan flip-flop further comprises (1) a master latch configured to latch data selected by the multiplexer, wherein an input of the master latch is coupled to an output of the multiplexer, (2) a switch controlled by clock signals, wherein an input of the switch is coupled to an output of the master latch, and (3) a slave latch configured to latch data from the master latch. An input of the slave latch is coupled to an output of the switch, and the slave latch comprises a tri-state inverter controlled by clock signals. The tri-state inverter of the slave latch is configured to supply current to the multiplexer when the tri-state inverter is enabled by the clock signals.
