18167369. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18167369 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes a base substrate, an interposer substrate, connection bumps, underfill resin, and two semiconductor chips.
- The interposer substrate has a first surface facing the base substrate and a second surface, with a passivation layer on at least a portion of the first surface.
- Connection bumps are present between the base substrate and the interposer substrate, allowing for electrical connections.
- An underfill resin fills the space between the base substrate and the interposer substrate, providing structural support and protection.
- The interposer substrate has different regions, including a first region with connection bumps and second and third regions adjacent to the periphery of the first region.
- The passivation layer on the second region of the interposer substrate includes a first embossed pattern.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- High-performance computing systems and servers.
- Automotive electronics and advanced driver-assistance systems (ADAS).
- Internet of Things (IoT) devices and sensors.
Problems solved by this technology:
- Provides a reliable and efficient method for connecting semiconductor chips to a base substrate.
- Offers improved structural integrity and protection for the semiconductor package.
- Reduces the risk of electrical shorts and other failures.
- Enables higher-density packaging and miniaturization of electronic devices.
Benefits of this technology:
- Enhanced electrical connectivity and performance.
- Improved reliability and durability of semiconductor packages.
- Enables smaller and more compact electronic devices.
- Cost-effective manufacturing process for semiconductor packaging.
Original Abstract Submitted
A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.
