18163986. METAL GATE PATTERNING simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

METAL GATE PATTERNING

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Tefu Yeh of Kaohsiung (TW)

Cheng-Chieh Tu of Hsinchu (TW)

Hao-Hsin Chen of Keelung (TW)

Jo-Chun Hung of Hsinchu (TW)

Ying-Liang Chuang of Hsinchu (TW)

Ming-Hsi Yeh of Hsinchu (TW)

Kuo-Bin Huang of Hsinchu (TW)

METAL GATE PATTERNING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18163986 titled 'METAL GATE PATTERNING

The method described in the patent application involves forming gate structures for n-type and p-type transistors using specific steps and materials.

• Forming an interfacial layer and high-K dielectric layer for the gate structures
• Depositing an n-type metal layer over the high-K dielectric layer
• Applying a hard capping layer over the n-type metal layer while strengthening the high-K dielectric layer with fluorine passivation
• Patterning photoresist material to expose a portion of the hard capping layer over the p-type transistor
• Removing the n-type metal layer and hard capping layer over the p-type transistor through wet etching operations with high selectivity chemicals
• Insulating gate structures from aluminum oxidation by removing the patterned photoresist material
• Depositing a p-type metal layer over the hard capping layer and the p-type transistor

This method aims to improve the performance and reliability of transistors by enhancing the gate structures for both n-type and p-type devices.

Potential Applications: - Semiconductor manufacturing - Integrated circuit design - Electronics industry

Problems Solved: - Enhancing gate structure performance - Improving transistor reliability - Reducing oxidation effects

Benefits: - Increased transistor efficiency - Enhanced device longevity - Improved overall device performance

Commercial Applications: Title: Advanced Gate Structure Formation Method for Transistors This technology could be utilized in the production of high-performance electronic devices, leading to improved functionality and durability in various consumer electronics and industrial applications.

Questions about the technology: 1. How does the use of a hard capping layer benefit the gate structures in transistors? 2. What are the specific advantages of using fluorine passivation in strengthening the high-K dielectric layer?

Original Abstract Submitted

Disclosed is a method of forming gate structures for n-type and p-type transistors. The method includes: forming an interfacial layer and high-K (HK) dielectric layer for the gate structures; forming an n-type metal layer over the HK dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the HK dielectric layer by fluorine passivation; patterning photo resist (PR) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned PR material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.