18163584. WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM) simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM)
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM) - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM)
Organization Name
Inventor(s)
Poornima Venkatasubramanian of Bengaluru (IN)
Pushp Khatter of Bengaluru (IN)
Lava Kumar Pulluru of Bengaluru (IN)
Manish Chandra Joshi of Bengaluru (IN)
Anurag Kumar of Bengaluru (IN)
Surendra Deshmukh of Bengaluru (IN)
WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM) - A simplified explanation of the abstract
This abstract first appeared for US patent application 18163584 titled 'WRITE ASSIST CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY (SRAM)
Simplified Explanation
The write assist circuit described in the patent application includes two power control circuits, each comprising a first switch and a second switch. The first switches of both power control circuits have a first drive strength and are controlled by the column select line, power control line, bit lines, and power supply. The second switch has a second drive strength and is controlled by the power control line. These switches are used to alter the power supply to inverters in an SRAM bitcell based on input data.
- The write assist circuit includes two power control circuits with first and second switches.
- The first switches have a first drive strength and are controlled by various input lines and the power supply.
- The second switch has a second drive strength and is controlled by the power control line.
- The switches are used to adjust the power supply to inverters in an SRAM bitcell based on input data.
Potential Applications
The technology described in this patent application could be applied in:
- Memory devices
- Integrated circuits
- Computer systems
Problems Solved
This technology helps in:
- Improving write performance in SRAM bitcells
- Reducing power consumption
- Enhancing overall efficiency of memory devices
Benefits
The benefits of this technology include:
- Faster write operations in memory devices
- Lower power consumption leading to energy efficiency
- Improved reliability and performance of integrated circuits
Potential Commercial Applications
The write assist circuit technology could be utilized in various commercial applications such as:
- Consumer electronics
- Automotive electronics
- Industrial automation systems
Possible Prior Art
One possible prior art related to this technology is the use of write assist circuits in memory devices to improve write performance and reduce power consumption.
Unanswered Questions
How does the write assist circuit impact the overall speed of memory devices?
The article does not delve into the specific impact of the write assist circuit on the speed of memory devices. This could be an important factor for potential users looking to understand the full scope of benefits.
Are there any limitations to the write assist circuit technology in terms of scalability to different memory device sizes?
The article does not address any potential limitations or challenges related to scaling the write assist circuit technology to different sizes of memory devices. Understanding these limitations could be crucial for manufacturers considering implementing this technology.
Original Abstract Submitted
A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.
