18158709. LOW POWER ARCHITECTURE FOR CHIPLETS simplified abstract (QUALCOMM Incorporated)
Contents
LOW POWER ARCHITECTURE FOR CHIPLETS
Organization Name
Inventor(s)
Praveen Raghuraman of Chennai (IN)
Vivek Roopchand of Chennai (IN)
Karthikeyan Soundararajan of Chennai (IN)
LOW POWER ARCHITECTURE FOR CHIPLETS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18158709 titled 'LOW POWER ARCHITECTURE FOR CHIPLETS
The patent application describes a method for communicating test information within a semiconductor circuit block.
- Data stream is provided to a circuit block on a semiconductor die.
- Data channels are demultiplexed from the data stream.
- Test information collected from various sections of the circuit block is inserted into data channels by embedded distributed test circuits.
- The data channels are multiplexed to create a modified data stream.
- The modified data stream is transmitted to another circuit block on the semiconductor die.
Potential Applications: - Semiconductor testing and debugging processes - Improving efficiency and accuracy of test information collection - Enhancing communication within complex semiconductor systems
Problems Solved: - Streamlining test information communication within semiconductor circuits - Facilitating the collection and transmission of data in a structured manner
Benefits: - Increased efficiency in testing processes - Enhanced reliability of test information - Improved overall performance of semiconductor systems
Commercial Applications: Title: "Advanced Semiconductor Testing and Communication Technology" This technology can be utilized in the semiconductor manufacturing industry to streamline testing processes, improve communication within complex circuits, and enhance overall system performance. It can be integrated into various semiconductor devices to ensure efficient and accurate testing procedures, ultimately leading to higher quality products and increased customer satisfaction.
Questions about the technology: 1. How does this method improve the efficiency of semiconductor testing processes? - By utilizing embedded distributed test circuits to collect and insert test information into data channels, the method ensures a structured and organized approach to communication within the circuit block, leading to more efficient testing procedures.
2. What are the potential implications of implementing this technology in semiconductor manufacturing? - Implementing this technology can lead to improved testing accuracy, faster debugging processes, and overall enhanced performance of semiconductor systems, which can have significant implications for the industry in terms of product quality and customer satisfaction.
Original Abstract Submitted
A method for communicating test information, includes providing a data stream to a circuit block that is implemented on a semiconductor die, demultiplexing data channels from the data stream, multiplexing the data channels to obtain a modified data stream after test information collected from a plurality of sections of the circuit block has been inserted into one or more data channels allocated to at least one section of the circuit block by corresponding embedded distributed test (EDT) circuits implemented in the at least one section of the circuit block, and transmitting the modified data stream to another circuit block implemented on the semiconductor die.
