18150155. Low Power Memory System Using Dual Input-Output Voltage Supplies simplified abstract (QUALCOMM Incorporated)

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Low Power Memory System Using Dual Input-Output Voltage Supplies

Organization Name

QUALCOMM Incorporated

Inventor(s)

Jungwon Suh of San Diego CA (US)

Joon Young Park of San Diego CA (US)

Mahalingam Nagarajan of San Diego CA (US)

Low Power Memory System Using Dual Input-Output Voltage Supplies - A simplified explanation of the abstract

This abstract first appeared for US patent application 18150155 titled 'Low Power Memory System Using Dual Input-Output Voltage Supplies

Simplified Explanation

The abstract describes a memory system in a computing device that uses a 3 level pulse amplitude modulation (PAM) IO scheme to communicate data during a memory transaction. The system includes a memory device, a memory physical layer, and two voltage supplies.

  • The memory system uses a memory device and a memory physical layer to communicate data.
  • The system employs a 3 level pulse amplitude modulation (PAM) IO scheme for data transmission.
  • A first input/output (IO) voltage supply is connected to the memory device and the memory physical layer.
  • A second TO voltage supply is also connected to the memory device and the memory physical layer.

Potential applications of this technology:

  • Memory systems in computing devices such as computers, smartphones, and tablets.
  • Data storage and retrieval in various industries including cloud computing, data centers, and artificial intelligence.

Problems solved by this technology:

  • Efficient and reliable communication of data during memory transactions.
  • Improved performance and speed of memory systems.

Benefits of this technology:

  • Enhanced data transmission using the 3 level pulse amplitude modulation (PAM) IO scheme.
  • Increased efficiency and reliability of memory systems.
  • Improved overall performance and speed of computing devices.


Original Abstract Submitted

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

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