18149072. METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS simplified abstract (Intel Corporation)

METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS

Organization Name

Intel Corporation

Inventor(s)

Deepak Samuel Kirubakaran of Hillsboro OR (US)

Rajshree Chabukswar of Sunnyvale CA (US)

Zhongsheng Wang of Camas WA (US)

Russell Fenger of Beaverton OR (US)

Asit Kumar Verma of Bangalore (IN)

DK Deepika of Secunderabad (IN)

Yevgeni Sabin of Haifa (IL)

Daniel J. Rogers of Folsom CA (US)

Cameron T. Rieck of Portland OR (US)

METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18149072 titled 'METHODS, SYSTEMS, AND APPARATUSES FOR DYNAMIC SIMULTANEOUS MULTI-THREADING (SMT) SCHEDULING TO MAXIMIZE PROCESSOR PERFORMANCE ON HYBRID PLATFORMS

Simplified Explanation: The patent application describes techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platform.

• The hardware processor includes two types of physical processor cores, each capable of implementing multiple logical processor cores.
• The circuitry determines if a set of threads from a foreground application requires a specific number of logical processor cores and adjusts the core activation accordingly.

Key Features and Innovation:

• Hybrid processor platform with multiple types of physical processor cores.
• Dynamic SMT scheduling based on thread requirements.
• Ability to disable specific logical processor cores based on thread needs.

Potential Applications:

• High-performance computing systems.
• Server environments with varying workload demands.
• Cloud computing platforms.

Problems Solved:

• Efficient utilization of processor resources.
• Optimization of core activation based on thread requirements.
• Improved performance in multi-threaded applications.

Benefits:

• Enhanced performance in diverse workload scenarios.
• Resource optimization for better power efficiency.
• Scalability for varying computational demands.

Commercial Applications: Dynamic SMT scheduling technology can be utilized in data centers, cloud computing services, and high-performance computing clusters to optimize resource allocation and improve overall system performance.

Prior Art: Prior research in the field of processor scheduling algorithms and multi-threading techniques may provide insights into similar approaches to dynamic core activation based on workload requirements.

Frequently Updated Research: Stay updated on the latest advancements in processor scheduling algorithms, multi-threading optimizations, and hybrid processor architectures to enhance the efficiency and performance of computing systems.

Questions about dynamic simultaneous multi-threading (SMT) scheduling: 1. How does dynamic SMT scheduling improve processor performance in multi-threaded applications? 2. What are the key considerations when implementing dynamic core activation based on thread requirements?

Original Abstract Submitted

Techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platforms are described. In certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g., a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type), and disable a second logical core of a physical processor core of the second type, and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads of the foreground application is to use more than the lower threshold number of logical processor cores and less than or equal to the upper threshold (e.g., the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type).