18147099. FLEXIBLE VECTORIZED PROCESSING ARCHITECTURE simplified abstract (Intel Corporation)
Contents
FLEXIBLE VECTORIZED PROCESSING ARCHITECTURE
Organization Name
Inventor(s)
Jian-Guo Chen of Basking Ridge NJ (US)
David Dougherty of Allentown PA (US)
Madihally Narasimha of Saratoga CA (US)
Joseph Othmer of Ocean NJ (US)
Joseph Williams of Holmdel NJ (US)
Zoran Zivkovic of Hertogenbosch (NL)
FLEXIBLE VECTORIZED PROCESSING ARCHITECTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18147099 titled 'FLEXIBLE VECTORIZED PROCESSING ARCHITECTURE
The patent application describes techniques for a programmable processing array architecture that enables vectorized processing operations for various applications, including digital front end (DFE) processing operations such as FIR filter processing.
- The architecture includes a front-end interconnection network that generates specific data sliding time window patterns based on the DFE processing operation to be executed.
- Processed data is fed to a set of multipliers and adders to generate output data, supporting a wide range of processing operations through a single programmable processing array platform.
- Leveraging the programmable nature of the array and instruction sets, the architecture enables efficient execution of complex processing tasks.
Potential Applications: - Signal processing applications - Wireless communication systems - Radar systems - Image and video processing
Problems Solved: - Efficient execution of vectorized processing operations - Flexibility in adapting to different processing tasks - Streamlined processing of data in real-time applications
Benefits: - Improved performance and efficiency in processing operations - Versatility in handling diverse processing tasks - Scalability for future technological advancements
Commercial Applications: Title: Programmable Processing Array Architecture for Advanced Signal Processing This technology can be utilized in various industries such as telecommunications, defense, and multimedia for enhancing signal processing capabilities and improving overall system performance.
Questions about the technology: 1. How does the programmable processing array architecture improve processing efficiency? - The architecture optimizes processing tasks by generating specific data patterns and utilizing multipliers and adders effectively. 2. What are the key advantages of using a programmable processing array platform for vectorized processing operations? - The platform offers flexibility, scalability, and performance enhancements for a wide range of applications.
Original Abstract Submitted
Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.
