18129559. COHERENT MEMORY ACCESS simplified abstract (Micron Technology, Inc.)
Contents
COHERENT MEMORY ACCESS
Organization Name
Inventor(s)
Timothy P. Finkbeiner of Boise ID (US)
Troy D. Larsen of Meridian ID (US)
COHERENT MEMORY ACCESS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18129559 titled 'COHERENT MEMORY ACCESS
The abstract describes an apparatus and method for providing coherent memory access, involving a memory array, processing resources, cache lines, and cache controllers.
- The apparatus includes a memory array, processing resources, cache lines, and cache controllers.
- The cache controllers are configured to provide coherent access to data stored in different cache lines corresponding to a memory address.
- Coherent access is achieved through address registers in the cache controllers storing the memory address.
Potential Applications: - This technology can be used in computer systems to improve memory access efficiency. - It can enhance the performance of multi-core processors by ensuring coherent data access.
Problems Solved: - Ensures data consistency and coherence in memory access. - Optimizes memory access in complex computing systems.
Benefits: - Improved performance and efficiency in memory access. - Enhanced reliability and consistency in data retrieval.
Commercial Applications: Title: "Enhancing Memory Access Efficiency in Computer Systems" This technology can be applied in servers, data centers, and high-performance computing systems to optimize memory access and improve overall system performance.
Questions about Coherent Memory Access: 1. How does coherent memory access improve data consistency in computer systems? 2. What are the key components of an apparatus for providing coherent memory access?
Frequently Updated Research: Stay updated on the latest advancements in memory access optimization and coherent data retrieval techniques to enhance system performance.
Original Abstract Submitted
Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.
