18103201. INTEGRATION SCHEME FOR FABRICATING HIGH PRECISION, LOW CAPACITOR WITH UNLANDED VIA simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 INTEGRATION SCHEME FOR FABRICATING HIGH PRECISION, LOW CAPACITOR WITH UNLANDED VIA
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 INTEGRATION SCHEME FOR FABRICATING HIGH PRECISION, LOW CAPACITOR WITH UNLANDED VIA - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Key Features and Innovation
- 1.6 Potential Applications
- 1.7 Problems Solved
- 1.8 Benefits
- 1.9 Commercial Applications
- 1.10 Prior Art
- 1.11 Frequently Updated Research
- 1.12 Questions about Semiconductor Device Fabrication with Capacitors
- 1.13 Original Abstract Submitted
INTEGRATION SCHEME FOR FABRICATING HIGH PRECISION, LOW CAPACITOR WITH UNLANDED VIA
Organization Name
Inventor(s)
Sunil Kumar Singh of Round Rock TX (US)
Sivashankar Sivasubramanian of Austin TX (US)
INTEGRATION SCHEME FOR FABRICATING HIGH PRECISION, LOW CAPACITOR WITH UNLANDED VIA - A simplified explanation of the abstract
This abstract first appeared for US patent application 18103201 titled 'INTEGRATION SCHEME FOR FABRICATING HIGH PRECISION, LOW CAPACITOR WITH UNLANDED VIA
Simplified Explanation
The patent application describes a method for fabricating semiconductor devices with capacitors. It involves forming layers of dielectric materials and metal to create the capacitor structure.
- Metal is patterned on a substrate within a dielectric material to form the first metal surface of the capacitor.
- Multiple dielectric layers are formed above the metal layer.
- A supervia is etched through the upper dielectric layer and into the middle layer, hanging in the second dielectric material above the patterned metal.
- Barrier deposition and metal electroplating are performed in the supervia to create the second metal surface of the capacitor.
Key Features and Innovation
- Fabrication method for semiconductor devices with capacitors.
- Formation of multiple dielectric layers and metal surfaces.
- Use of supervia for creating the capacitor structure.
Potential Applications
The technology can be applied in the semiconductor industry for manufacturing advanced electronic devices with capacitors.
Problems Solved
The method addresses the need for efficient fabrication processes for semiconductor devices with capacitors.
Benefits
- Improved performance of semiconductor devices.
- Enhanced capacitance and functionality.
- Cost-effective manufacturing process.
Commercial Applications
- Semiconductor manufacturing industry for electronic devices.
- Consumer electronics market for improved products with capacitors.
Prior Art
Information on prior methods of fabricating semiconductor devices with capacitors may be available in related patents or research papers.
Frequently Updated Research
Any new developments or research in semiconductor device fabrication methods, particularly those involving capacitors, would be relevant to this technology.
Questions about Semiconductor Device Fabrication with Capacitors
Question 1
How does the use of multiple dielectric layers enhance the performance of the capacitor in semiconductor devices?
Multiple dielectric layers improve the insulation and capacitance of the capacitor, leading to better overall performance in semiconductor devices.
Question 2
What are the potential challenges in implementing the supervia technique for creating the capacitor structure in semiconductor devices?
Implementing the supervia technique may require precise etching and deposition processes, which could pose challenges in terms of control and uniformity in manufacturing.
Original Abstract Submitted
Semiconductor devices including a capacitor and methods of fabricating the semiconductor devices are disclosed. A method of fabricating a semiconductor device including a capacitor includes forming an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; etching a supervia though the upper layer and into the middle layer, wherein the supervia hangs in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating in the supervia, wherein the supervia forms a second metal surface of the capacitor above the first metal surface.
