18101246. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Kihong Jeong of Jeonju-si (KR)

Sangsub Song of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18101246 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The patent application describes a semiconductor package that includes a package substrate, a processor chip, and multiple memory chips stacked on the package substrate. There are two stack structures: the first stack structure includes M memory chips stacked on the processor chip, and the second stack structure includes N memory chips stacked on the package substrate.

• The number of channels connecting the memory chips in the second stack structure to the processor chip (Q) may be greater than the number of channels connecting the memory chips in the first stack structure to the processor chip (P).
• Alternatively, the number of memory chips in the second stack structure (N) may be greater than the number of memory chips in the first stack structure (M).

Potential Applications:

• This technology can be applied in various electronic devices that require high-performance memory systems, such as smartphones, tablets, and computers.
• It can also be used in data centers and servers to enhance processing and memory capabilities.

Problems Solved:

• The semiconductor package addresses the need for increased memory capacity and improved data transfer rates in electronic devices.
• It solves the challenge of efficiently connecting multiple memory chips to a processor chip.

Benefits:

• The increased number of channels or memory chips allows for faster data transfer and improved overall performance.
• The stacked structure optimizes space utilization, enabling higher memory capacity within a compact package.
• The technology offers flexibility in designing semiconductor packages to meet specific memory and processing requirements.

Original Abstract Submitted

A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.