18092091. FREQUENCY MULTIPLIER CALIBRATION simplified abstract (TEXAS INSTRUMENTS INCORPORATED)

FREQUENCY MULTIPLIER CALIBRATION

Organization Name

TEXAS INSTRUMENTS INCORPORATED

Inventor(s)

Michael Henderson Perrott of Nashua NH (US)

FREQUENCY MULTIPLIER CALIBRATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18092091 titled 'FREQUENCY MULTIPLIER CALIBRATION

Simplified Explanation:

The patent application describes an apparatus that includes a delay-based frequency multiplier and an error detection circuit. The frequency multiplier generates a multiplied clock signal with adjustable delay, while the error detection circuit detects timing errors in the clock signal.

• The apparatus includes a delay-based frequency multiplier and an error detection circuit.
• The frequency multiplier produces a multiplied clock signal with adjustable delay.
• The error detection circuit identifies timing errors in the clock signal.
• The error detection circuit adjusts the delay of the frequency multiplier based on detected errors.
• The apparatus aims to improve the accuracy and reliability of clock signals in electronic systems.

Potential Applications:

This technology could be used in various electronic devices and systems where precise timing is critical, such as communication systems, data processing units, and signal processing applications.

Problems Solved:

This technology addresses issues related to clock signal accuracy and timing errors in electronic systems, ensuring reliable operation and improved performance.

Benefits:

The benefits of this technology include enhanced accuracy of clock signals, reduced timing errors, improved system reliability, and optimized performance of electronic devices.

Commercial Applications:

Potential commercial applications of this technology include telecommunications equipment, computer hardware, industrial automation systems, and other electronic devices requiring precise timing control.

Questions about the Technology: 1. How does the error detection circuit detect timing errors in the clock signal? 2. What are the key advantages of using a delay-based frequency multiplier in electronic systems?

Original Abstract Submitted

In some examples, an apparatus includes a delay-based frequency multiplier and an error detection circuit. The delay-based frequency multiplier has a clock input, a multiplier clock output, and a delay calibration input. The error detection circuit has a detection input and a detection output. The detection input is coupled to the multiplier clock output, and the detection output is coupled to the delay calibration input. The error detection circuit is configured to receive a clock signal at the detection input, and provide a period error signal at the detection output based on a time difference between a first edge of the clock signal and a second edge of a delayed version of the clock signal.