18092081. CHIP PACKAGE STRUCTURES, MANUFACTURING METHODS THEREOF AND ELECTRONIC DEVICES simplified abstract (Yangtze Memory Technologies Co., Ltd.)
Contents
- 1 CHIP PACKAGE STRUCTURES, MANUFACTURING METHODS THEREOF AND ELECTRONIC DEVICES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 CHIP PACKAGE STRUCTURES, MANUFACTURING METHODS THEREOF AND ELECTRONIC DEVICES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
CHIP PACKAGE STRUCTURES, MANUFACTURING METHODS THEREOF AND ELECTRONIC DEVICES
Organization Name
Yangtze Memory Technologies Co., Ltd.
Inventor(s)
CHIP PACKAGE STRUCTURES, MANUFACTURING METHODS THEREOF AND ELECTRONIC DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18092081 titled 'CHIP PACKAGE STRUCTURES, MANUFACTURING METHODS THEREOF AND ELECTRONIC DEVICES
Simplified Explanation
The disclosed semiconductor structure includes a package substrate, a first chip, a conductive pillar, and a second chip. The first chip is located on the package substrate and electrically connected to it, while the conductive pillar is also connected to the package substrate. The second chip is located on a side of the first chip and the conductive pillar, away from the package substrate, and is electrically connected to the conductive pillar. The structure is designed for connection with a circuit board in an electronic device.
- Package substrate with first chip, conductive pillar, and second chip
- First chip and conductive pillar electrically connected to package substrate
- Second chip connected to conductive pillar
- Designed for connection with circuit board in electronic device
Potential Applications
The semiconductor structure could be used in various electronic devices such as smartphones, tablets, laptops, and other consumer electronics where compact and efficient chip packaging is required.
Problems Solved
This technology solves the problem of efficiently connecting multiple chips in a compact space while ensuring proper electrical connections and signal integrity.
Benefits
The benefits of this technology include improved space utilization, enhanced electrical connectivity, and overall better performance of electronic devices.
Potential Commercial Applications
The semiconductor structure could find applications in the semiconductor industry, electronics manufacturing, and consumer electronics market. A potential commercial application could be in the development of advanced smartphones with multiple chips for improved performance.
Possible Prior Art
One possible prior art could be the use of stacked chip packages in electronic devices to save space and improve performance. Another could be the use of conductive pillars for electrical connections in semiconductor structures.
Unanswered Questions
How does this technology compare to existing chip packaging solutions in terms of cost-effectiveness and performance?
This article does not provide a direct comparison with existing chip packaging solutions in terms of cost-effectiveness and performance. It would be interesting to see a detailed analysis of these aspects to understand the competitive advantages of this technology.
What are the potential challenges in implementing this semiconductor structure in mass production?
The article does not address the potential challenges in implementing this semiconductor structure in mass production. It would be important to consider factors such as scalability, manufacturing complexity, and cost implications when moving towards large-scale production.
Original Abstract Submitted
In one example, the disclosed semiconductor structure includes a package substrate, a first chip, a conductive pillar and a second chip, wherein the package substrate has a first surface; the first chip is located on the first surface of the package substrate and electrically connected to the package substrate; the conductive pillar is located on the first surface of the package substrate and electrically connected to the package substrate; the second chip is located on a side of the first chip and the conductive pillar away from the package substrate and electrically connected to the conductive pillar; and an orthographic projection of the conductive pillar on the package substrate is located within a range of an orthographic projection of the first chip or the second chip on the package substrate. The chip package structure is configured for connection with a circuit board in the electronic device. Other examples are disclosed.
