18088552. INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CAPACITORS simplified abstract (Intel Corporation)
Contents
INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CAPACITORS
Organization Name
Inventor(s)
Abhishek Anil Sharma of Portland OR (US)
Tahir Ghani of Portland OR (US)
Anand S. Murthy of Portland OR (US)
Wilfred Gomes of Portland OR (US)
Pushkar Ranade of San Jose CA (US)
Sagar Suthram of Portland OR (US)
INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CAPACITORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18088552 titled 'INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CAPACITORS
The abstract describes structures with backside capacitors in an integrated circuit.
- Front side structure includes device layer with select transistors, metallization layers, and vias.
- Backside structure below vias includes memory layer connected to select transistors via vias.
Potential Applications: - Memory storage in integrated circuits - High-density data storage applications
Problems Solved: - Increased memory capacity in integrated circuits - Improved data processing speed
Benefits: - Enhanced performance of integrated circuits - Efficient data storage and retrieval
Commercial Applications: Title: Advanced Memory Storage Solutions This technology can be used in: - Consumer electronics - Data centers - Telecommunications industry
Questions about Backside Capacitors: 1. How do backside capacitors improve the performance of integrated circuits? Backside capacitors enhance memory capacity and data processing speed by providing additional storage capabilities.
2. What are the potential challenges associated with implementing backside capacitors in integrated circuits? Integrating backside capacitors may require additional design considerations and manufacturing processes to ensure proper functionality and performance.
Original Abstract Submitted
Structures having backside capacitors are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of select transistors, a plurality of metallization layers above the plurality of select transistors, and a plurality of vias below and coupled to the plurality of select transistors. A backside structure is below the plurality of vias of the device layer. The backside structure includes a memory layer coupled to the plurality of select transistors by the plurality of vias.
