18082518. RULER-FOLLOWER DYNAMIC VOLTAGE AND FREQUENCY SCALING SCHEMES FOR INTEGRATED CIRCUIT COMPONENTS simplified abstract (QUALCOMM Incorporated)
Contents
RULER-FOLLOWER DYNAMIC VOLTAGE AND FREQUENCY SCALING SCHEMES FOR INTEGRATED CIRCUIT COMPONENTS
Organization Name
Inventor(s)
Aravind Bhaskara of San Diego CA (US)
Zhurang Zhao of San Diego CA (US)
Kiran Bhagwat of San Diego CA (US)
Michael Tipton of Midlothian VA (US)
Joshua Stubbs of Longmont CO (US)
Jyotirmoy Das of San Diego CA (US)
Thomas Tang of Pleasanton CA (US)
RULER-FOLLOWER DYNAMIC VOLTAGE AND FREQUENCY SCALING SCHEMES FOR INTEGRATED CIRCUIT COMPONENTS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18082518 titled 'RULER-FOLLOWER DYNAMIC VOLTAGE AND FREQUENCY SCALING SCHEMES FOR INTEGRATED CIRCUIT COMPONENTS
Simplified Explanation:
This patent application discusses various techniques for dynamic voltage and frequency scaling (DVFS) to optimize the high voltage residency of a device with multiple processing cores sharing a voltage rail. By aligning the high frequency duration of these cores, the techniques aim to reduce the duration of high voltage residency.
- The patent application focuses on optimizing the high voltage residency of a device with multiple processing cores that share a voltage rail.
- Various dynamic voltage and frequency scaling (DVFS) techniques are proposed to achieve this optimization.
- The techniques aim to reduce the duration of high voltage residency by aligning the high frequency duration of the processing cores.
- By implementing these DVFS techniques, the overall power consumption of the device can be reduced while maintaining performance levels.
- The innovation lies in the specific methods used to coordinate the frequency scaling of multiple cores to minimize high voltage residency.
Potential Applications: The technology described in this patent application could be applied in:
- Mobile devices
- Internet of Things (IoT) devices
- Embedded systems
- High-performance computing systems
Problems Solved: This technology addresses the following problems:
- High power consumption in devices with multiple processing cores
- Inefficient use of voltage rails in shared-core devices
- Performance degradation due to high voltage residency
Benefits: The benefits of this technology include:
- Improved energy efficiency
- Enhanced performance optimization
- Extended battery life in mobile devices
- Reduced heat generation in high-performance computing systems
Commercial Applications: Title: "Optimizing High Voltage Residency in Multi-Core Devices" This technology could have commercial applications in:
- Smartphone and tablet manufacturing
- IoT device development
- Data center management
- Semiconductor industry
Prior Art: Readers interested in prior art related to this technology can explore research papers, patents, and industry publications on dynamic voltage and frequency scaling techniques in multi-core devices.
Frequently Updated Research: Researchers are continually exploring new DVFS techniques and optimizations for multi-core devices. Stay updated on the latest advancements in this field for potential improvements in energy efficiency and performance optimization.
Questions about Dynamic Voltage and Frequency Scaling: 1. How does dynamic voltage and frequency scaling impact the overall power consumption of a device?
- Answer: DVFS allows devices to adjust their voltage and frequency levels based on workload, leading to energy savings without compromising performance.
2. What are the key challenges in implementing DVFS techniques in devices with multiple processing cores?
- Answer: Coordinating the frequency scaling of multiple cores to minimize high voltage residency and maintain performance levels is a significant challenge in multi-core devices.
Original Abstract Submitted
Various dynamic voltage and frequency scaling (DVFS) techniques can optimize the high voltage residency of a device containing multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce the high voltage residency (duration) of the voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.
