18077809. TWO STEP IMPLANT TO IMPROVE LINE EDGE ROUGHNESS AND LINE WIDTH ROUGHNESS simplified abstract (Applied Materials, Inc.)
Contents
TWO STEP IMPLANT TO IMPROVE LINE EDGE ROUGHNESS AND LINE WIDTH ROUGHNESS
Organization Name
Inventor(s)
John Hautala of Beverly MA (US)
Huixiong Dai of San Jose CA (US)
TWO STEP IMPLANT TO IMPROVE LINE EDGE ROUGHNESS AND LINE WIDTH ROUGHNESS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18077809 titled 'TWO STEP IMPLANT TO IMPROVE LINE EDGE ROUGHNESS AND LINE WIDTH ROUGHNESS
Simplified Explanation: The patent application describes a method to reduce line edge roughness and line width roughness on a semiconductor workpiece by performing two high-tilt angle implants using different species of ions on the patterned photoresist before the etching process.
- Two high-tilt angle implants using different species of ions are performed on the patterned photoresist.
- Implants are done at twist angles to make the ion trajectory nearly parallel to the photoresist lines, reducing roughness.
- Glancing ions from the implants smooth the top and sidewalls of the photoresist lines, minimizing impact on critical dimensions (CD).
Potential Applications: This technology can be applied in semiconductor manufacturing processes to improve the quality and precision of patterned photoresist on workpieces.
Problems Solved: The method addresses the issues of line edge roughness and line width roughness that can affect the performance and functionality of semiconductor devices.
Benefits: - Enhanced precision and quality of patterned photoresist - Reduction in line edge roughness and line width roughness - Minimal impact on critical dimensions
Commercial Applications: Title: Advanced Semiconductor Manufacturing Process for Enhanced Precision This technology can be utilized in the semiconductor industry for producing high-quality and precise semiconductor devices, improving overall performance and reliability.
Prior Art: Prior research in semiconductor manufacturing and ion implantation techniques may provide insights into similar methods for reducing roughness in patterned photoresist.
Frequently Updated Research: Ongoing research in semiconductor fabrication processes and ion implantation technologies may offer advancements in reducing roughness in patterned photoresist for improved semiconductor device performance.
Questions about the Technology: 1. How does the method of high-tilt angle implants differ from traditional techniques in reducing line edge roughness? 2. What are the potential implications of this technology on the overall yield and efficiency of semiconductor manufacturing processes?
Original Abstract Submitted
Methods of processing patterned photoresist to reduce line edge roughness and line width roughness on a semiconductor workpiece are disclosed. The method is performed after the photoresist has been patterned and before the etching process is commenced. Two implants, using different species, are performed at high tilt angles. In certain embodiments, the tilt angle may be 45° or more. Further, the implants are performed at twist angles such that the trajectory of the ions is nearly parallel to the patterned photoresist lines. In this way, the ions from the two implants glance the top and sidewalls of the photoresist lines. Using this technique, the LER and LWR of the photoresist lines may be reduced with minimal impact on the CD.
