18072201. LOCOS FILLET FOR DRAIN REDUCED BREAKDOWN IN HIGH VOLTAGE TRANSISTORS simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
Contents
- 1 LOCOS FILLET FOR DRAIN REDUCED BREAKDOWN IN HIGH VOLTAGE TRANSISTORS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 LOCOS FILLET FOR DRAIN REDUCED BREAKDOWN IN HIGH VOLTAGE TRANSISTORS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
LOCOS FILLET FOR DRAIN REDUCED BREAKDOWN IN HIGH VOLTAGE TRANSISTORS
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Martin B. Mollat of Gainesville TX (US)
Henry L. Edwards of Garland TX (US)
Alexei Sadovnikov of Sunnyvale CA (US)
LOCOS FILLET FOR DRAIN REDUCED BREAKDOWN IN HIGH VOLTAGE TRANSISTORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18072201 titled 'LOCOS FILLET FOR DRAIN REDUCED BREAKDOWN IN HIGH VOLTAGE TRANSISTORS
Simplified Explanation
The integrated circuit described in the patent application involves a gate electrode, source region, drain region, and a dielectric layer with varying thicknesses and a fillet connecting different segments of the lateral perimeter.
- The integrated circuit includes a source region and a drain region spaced apart in a semiconductor layer.
- A gate electrode extends between the source and drain regions.
- A dielectric layer separates the gate electrode from the semiconductor layer.
- The dielectric layer has a first portion with a first thickness and a second portion with a greater second thickness.
- The second portion of the dielectric layer forms a lateral perimeter surrounding the source region.
- The lateral perimeter has a first edge with a linear segment along a first direction and a second edge with a linear segment along a different second direction.
- A fillet of the second portion connects the linear segments of the lateral perimeter.
Potential Applications
This technology could be applied in the development of advanced integrated circuits for various electronic devices, such as smartphones, computers, and other consumer electronics.
Problems Solved
This innovation helps in improving the performance and efficiency of integrated circuits by providing better control over the flow of electrical current between the source and drain regions.
Benefits
- Enhanced functionality and performance of electronic devices - Increased efficiency and reliability of integrated circuits - Potential for smaller and more compact electronic devices
Potential Commercial Applications
The technology could be utilized in the semiconductor industry for the production of high-performance integrated circuits, leading to the development of faster and more energy-efficient electronic devices.
Possible Prior Art
One possible prior art could be the use of different dielectric materials in integrated circuits to control the flow of electrical current and improve overall performance.
Unanswered Questions
How does this technology impact the overall cost of manufacturing integrated circuits?
The article does not provide information on the cost implications of implementing this technology in the production of integrated circuits.
What are the potential challenges in scaling this technology for mass production?
The article does not address the scalability of this technology and any challenges that may arise when trying to mass-produce integrated circuits using this innovation.
Original Abstract Submitted
An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter.